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Results: 1614

#	Item
631	Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu/flexram Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 11:50:27 Computer engineering Dynamic random-access memory CPU cache Random-access memory Processor-in-memory Cache Microarchitecture Memory hierarchy Computer memory Computer hardware Computing
632	Rare Time Series Motif Discovery from Unbounded Streams Nurjahan Begum Eamonn Keogh Add to Reading List Source URL: www.vldb.org Language: English - Date: 2014-09-10 17:59:50 Bloom filter Hashing Cache algorithms Bit array Random walk Sampling Data Cache-oblivious algorithm CPU cache Cache Statistics Computing
633	Novel Multimedia Instruction Capabilities in VLIW Media Processors J. T. J. van Eijndhoven 1,2 F. W. Sijstermans 1 (1) Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:48:47 Computing Parallel computing Very long instruction word TriMedia Instruction set CPU cache Slot Multiflow Computer architecture Computer hardware Central processing unit
634	______________QuicKit RISC Modules _ __________ MIPS PM4700 MIPS PM5000 Add to Reading List Source URL: www.cacdsp.com Language: English - Date: 2001-12-11 11:09:04 Instruction set architectures MIPS Technologies MIPS architecture R4600 R4000 Reduced instruction set computing R5000 64-bit CPU cache Computer hardware Computer architecture Computing
635	Doubling the Performance of Python/NumPy with less than 100 SLOC Simon A. F. Lund, Kenneth Skovhede, Mads R. B. Kristensen, and Brian Vinter Niels Bohr Institute, University of Copenhagen, Denmark {safl/skovhede/madsbk/v Add to Reading List Source URL: hiperfit.dk Language: English Computer memory Arrays NumPy CPU cache C dynamic memory allocation Benchmark Lookup table Computing Computer programming Cache
636	intel ® The i860™ XP Second Generation of the i860™ Supercomputing Microprocessor Family David Perlmutter Michael Kagan Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:44:33 Computer architecture Central processing unit Intel i860 CPU cache Microprocessor Supercomputer Vector processor Computing Computer hardware Parallel computing
637	IBM “MXT” Memory Compression Technology Debuts in a ServerWorks Northbridge R. Brett Tremaine Senior Technical Staff Member IBM, TJ Watson Research Center Yorktown Heights, NY Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:38:03 Digital media CPU cache DIMM DDR SDRAM Synchronous dynamic random-access memory Memory controller Dynamic random-access memory Dell Dimension Intel Xeon chipsets Computer memory Computer hardware Computing
638	Enhancing the B+-tree by Dynamic Node Popularity Caching + Cui Yu + James Bailey $ Julian Montefusco + Add to Reading List Source URL: www.ruizhang.info Language: English - Date: 2010-01-13 06:01:07 R-tree Data management B+ tree Cache Trie Tree Binary trees Distributed data storage CPU cache B-tree Graph theory Computing
639	UltraSparc IIi Kevin Normoyle and the Sabre cats One size doesn’t fit all Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:48:18 Cache Central processing unit UltraSPARC III Dynamic random-access memory Conventional PCI R8000 TurboSPARC Computer hardware Computer memory CPU cache
640	The Itanium™ Processor Cartridge Bill Samaras Itanium™ Processor Cartridge Design Manager Intel Corporation Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:38:10 Computer buses Itanium CPU cache Back-side bus Intel Core Intel Montecito Xeon Computer hardware Computer architecture Computing

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